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_______________ge ne ra l de sc ript ion the max154/max158 and mx7824/mx7828 are high- speed, multi-channel analog-to-digital converters (adcs). the max154 and mx7824 have four analog input channels, while the max158 and mx7828 have eight channels. conversion time for all devices is 2.5s. the max154/max158 also feature a 2.5v on-chip refer - ence, forming a complete high-speed data acquisitio n system. all four converters include a built-in track/hold, eliminat- ing the need for an external track/hold with many i nput signals. the analog input range is 0v to +5v, altho ugh the adc operates from a single +5v supply. microprocessor interfaces are simplified by the adc s ability to appear as a memory location or i/o port without the need for external logic. the data outputs use l atched, three-state buffer circuitry to allow direct connec tion to a microprocessor data bus or system input port. the mx7824 and mx7828 are pin compatible with analog devices ad7824 and ad7828. the max154 and max158, which feature internal references, are also compatible with these products. ________________________applic a t ions digital signal processing high-speed data acquisition telecommunications high-speed servo control audio instrumentation ____________________________fe a t ure s ? one-chip data acquisition system ? four or eight analog input channels ? 2.5s per channel conversion time ? internal 2.5v reference (max154/max158 only) ? built-in track/hold function ? 1 / 2 lsb error specification ? single +5v supply operation ? no external clock ? new space-saving ssop package ______________orde ring i nform a t ion m x 7 8 2 4 /m x 7 8 2 8 cm os, h igh-spe e d, 8 -bit adcs w it h m ult iple x e r ________________________________________________________________ maxim integrated products 1 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 v dd nc a0 a1 ain1 ain2 ain3 ain4 top view db7 ( ) are for max154/max158 only. db6 db5 db4 db2 db1 db0 tp (ref out) 16 15 14 13 9 10 11 12 cs rdy v ref + v ref - gnd int rd db3 dip/so/ssop max154 mx7824 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 ain7 ain8 v dd a0 ain3 ain4 ain5 ain6 a1 a2 db7 db6 db0 tp (ref out) ain1 ain2 20 19 18 17 9 10 11 12 db5 db4 cs rdy rd db3 db2 db1 dip/so/ssop max158 mx7828 16 15 13 14 v ref + v ref - gnd int ___________________________________________________ _______pin configura t ions ca ll t oll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 for fre e sa m ple s or lit e ra t ure . 19-0255; rev 2; 4/94 part mx7824 ln mx7824kn mx7824lcwg 0c to +70c 0c to +70c 0c to +70c temp. range pin-package 24 narrow plastic dip 24 narrow plastic dip 24 wide so mx7824kcwg mx7824lcag mx7824kcag 0c to +70c 0c to +70c 0c to +70c 24 wide so 24 ssop 24 ssop ordering information continued on last page. error (lsb) 1 / 2 1 1 / 2 1 1 / 2 1 downloaded from: http:///
m x 7 8 2 4 /m x 7 8 2 8 cm os, h igh-spe e d, 8 -bit adcs w it h m ult iple x e r 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +5v, v ref + = +5v, v ref - = gnd, mode 0, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended per iods may affect device reliability. supply voltage, vdd to gnd ......................... ...............0v, +10v voltage at any other pins......................gnd - 0.3v, v dd + 0.3v output current (ref out)........................... .......................30ma power dissipation (any package) to +75c .......... ..........450mw derate above +25c by .............................. ................6mw/c operating temperature ranges mx7824, mx7828 kn/ln/kcw_/lcw_.................................... ........0c to +70c bq/cq .............................................. ...............-40c to +85c tq/uq.............................................. ..............-55c to +125c storage temperature range .......................... ...-65c to +160c lead temperature (soldering, 10sec) ................ .............+300c input capacitance (note 4) c in 58 pf input low voltage v inl 0.8 v input high current i inh 1 a input low current i inl -1 a analog input current i ain 3 a slew rate, tracking sr 0.7 0.157 v/s input high voltage v inh 2.4 v any channel, ain = 0v to 5v output noise e n 200 v/rms capacitive load 0.01 f analog input voltage range a inr v ref -v ref + v analog input capacitance c ain 45 pf 1 max15_b, mx782_k/b/t parameter symbol min typ max units channel to channel mismatch 1/4 lsb no missing codes resolution 8 bits total unadjusted error (note 1) 1/2 lsb reference resistance 14 k v ref + input voltage range v ref -v dd v v ref - input voltage range gnd v ref + v resolution 8 bits output voltage ref out 2.47 2.50 2.53 v load regulation -6 -10 mv power-supply sensitivity 1 3 mv 40 70 40 70 temperature drift (note 3) 60 100 ppm/c conditions t a = +25c i l = 0ma to 10ma, t a = +25c max15_a, mx782_l/c/u v dd 5%, t a = +25c max15_c max15_e max15_m accuracy reference input reference outputmax154/max158 only (note 2) analog input logic inputs ( C r d C , C c s C , a0, a1, a2) downloaded from: http:///
electrical characteristics (v dd = +5v, v ref + = +5v, v ref - = gnd, mode 0, t a = t min to t max , unless otherwise noted.) timing characteristics (note 5) (v dd = +5v, v ref + = +5v, v ref - = gnd, mode 0, t a = t min to t max , unless otherwise noted.) note 1: total unadjusted error includes offset, full-scale, and linearity errors. note 2: specified with no external load unless otherwise no ted. note 3: temperature drift is defined as change in output vo ltage from +25c to t min or t max divided by (25 - t min ) or (t max - 25). note 4: guaranteed by design. note 5: all input control signals are specified with t r = t f = 20ns (10% to 90% of +5v) and timed from a 1.6v vo ltage level. note 6: measured with load circuits of figure 1 and defined as the time required for an output to cross 0.8v o r 2.4v. note 7: defined as the time required for the data lines to change 0.5v when loaded with the circuits of figure 2. m x 7 8 2 4 /m x 7 8 2 8 cm os, h igh-spe e d, 8 -bit adcs w it h m ult iple x e r _______________________________________________________________________________________ 3 (note 6) (note 6) c l = 50pf, r l = 5k (note 7) c l = 50pf conditions ns 60 t dh data hold time ns 40 75 t inth C r d C to C i n t C delay (mode 1) ns 0 t csh ns 0 t css C c s C to C r d C setup time C c s C to C r d C hold time ns 20 50 t acc2 data access time after C i n t C , mode 0 ns 85 t acc1 data access time after C r d C s 1.6 2.0 t crd conversion time (mode 0) ns 30 40 t rdy C c s C to rdy delay ns 0 t as multiplexer address setup time ns 30 t ah multiplexer address hold time units t a = +25c symbol parameter ns 500 t p delay time between conversions 500 70 100 0 0 60 110 2.4 60 0 35 max15_ _c/e mx782_k/l/b/c 600 70 100 0 0 70 120 2.8 60 0 40 max15_ _m mx782_t/u min max min max min typ max ns 60 600 t rd C r d C pulse width (mode 1) 80 500 80 400 db0Cdb7, C i n t C ; i out = -360a C c s C = C r d C = 2.4v 5v 5% for specified performance db0Cdb7, rdy; v out = 0v to v dd v dd = 5% conditions lsb 1/16 1/4 pss power-supply sensitivity v 4.0 v oh output high voltage mw 25 75 power dissipation ma 15 i dd supply current v 4.75 5.25 v dd supply voltage a 3 three-state output current pf 58 c out output capacitance (note 4) units min typ max symbol parameter db0Cdb7, C i n t C ; rdy 0.4 v 0.4 v ol output low voltage i out = 1.6ma i out = 2.6ma logic outputs power supply downloaded from: http:///
m x 7 8 2 4 /m x 7 8 2 8 cm os, h igh-spe e d, 8 -bit adcs w it h m ult iple x e r 4 _______________________________________________________________________________________ __________________________________________typic a l o pe ra t ing cha ra c t e rist ic s (t a = +25c, unless otherwise noted.) 2.520 2.480 -50 150 reference tem perature drift (m ax154/m ax158 only) 2.490 2.510 mx7824/28-1 ambient temperature (c) ref out voltage (v) 2.500 100 05 0 20 0 -100 150 output current vs. tem perature 4 12 16 mx7824/28-2 ambient temperature (c) output current (ma) 8 100 -50 0 50 v dd = 5v i source v out = 2.4v i sink v out = 0.4v 2.0 0 300 900 accuracy vs. delay between conversions (t p ) 0.5 1.0 1.5 mx7824/28-3 t p (ns) linearity error (lsb) 700 800 400 500 600 v dd = 5v v ref = 5v 2.0 0 05 accuracy vs. v ref (v ref = v ref + - v ref -) 0.5 1.0 1.5 mx7824/28-4 v ref (v) linearity error (lsb) 34 12 v dd = 5v 3k 3k 100pf dgnd dbn a. high-z to v oh b. high-z to v ol dbn +5v dgnd 100pf 3k 3k 10pf dgnd dbn a. v oh to high-z b. v ol to high-z dbn +5v dgnd 10pf 8 2 -100 150 power-supply current vs. tem perature (not including reference ladder) 3 4 5 6 7 mx7824/28-5 ambient temperature (c) i dd supply current (ma) 50 100 -50 0 v dd = 5.25v v dd = 5v v dd = 4.75v figure 1. load circuits for data-access time test figure 2. load circuits for data-hold time test downloaded from: http:///
m x 7 8 2 4 /m x 7 8 2 8 cm os, h igh-spe e d, 8 -bit adcs w it h m ult iple x e r _______________________________________________________________________________________ 5 reference output (2.5v) for max154. test point for mx7824. do not con nect. ref out tp 5 three-state data output, bit 0 (lsb) dbo 6 three-state data output, bit 1 db1 7 analog input channel 1 ain1 4 analog input channel 2 ain2 3 pin analog input channel 3 ain3 2 analog input channel 4 ain4 1 function name ___________________________________________________ __________pin de sc ript ions three-state data output, bit 2 db2 8 three-state data output, bit 3 db3 9 read input. C r d C controls conversions and data access. see digital interface section. C r d C 10 three-state data output, bit 7 (msb) db7 20 ground gnd 12 lower limit of reference span. sets the zero-code voltage. range: gnd to v ref +. v ref - 13 interrupt output. int going low indi- cates the completion of a conversion. see digital interface section. int 11 chip-select input. C c s C must be low for the device to be selected. C c s C 16 three-state data output, bit 4 db4 17 three-state data output, bit 5 db5 18 three-state data output, bit 6 db6 19 interrupt output. int going low indi- cates the completion of a conversion. see digital interface section. int 13 ground gnd 14 analog input channel 2 ain2 5 analog input channel 1 ain1 6 reference output (2.5v) for max158. test point for mx7828. do not connect. ref out tp 7 analog input channel 3 ain3 4 analog input channel 4 ain4 3 pin analog input channel 5 ain5 2 analog input channel 6 ain6 1 function name three-state data output, bit 0 (lsb) db0 8 three-state data output, bit 1 db1 9 three-state data output, bit 2 db2 10 three-state data output, bit 3 db3 11 lower limit of reference span. sets the zero-code voltage. range: gnd to v ref +. v ref - 15 read input. C r d C controls conversions and data access. see digital interface section. C r d C 12 ready output. open-drain output with no active pull-up device. goes low when C c s C goes low and high imped- ance at the end of a conversion. rdy 17 power-supply voltage, +5v v dd 26 channel address 2 input a2 23 channel address 1 input a1 24 channel address 0 input a0 25 upper limit of reference span. sets the full-scale input voltage. range: v ref - to v dd . v ref + 14 ready output. open-drain output with no active pull-up device. goes low when C c s C goes low and high imped- ance at the end of a conversion. rdy 15 power-supply voltage, +5v v dd 24 channel address 1 input a1 21 channel address 0 input a0 22 no connect nc 23 three-state data output, bit 7 (msb) db7 22 chip-select input. C c s C must be low for the device to be selected. C c s C 18 three-state data output, bit 4 db4 19 three-state data output, bit 5 db5 20 three-state data output, bit 6 db6 21 analog input channel 8 ain8 27 analog input channel 7 ain7 28 upper limit of reference span. sets the full-scale input voltage. range: v ref - to v dd . v ref + 16 max154 mx7824 max158 mx7828 downloaded from: http:///
m x 7 8 2 4 /m x 7 8 2 8 cm os, h igh-spe e d, 8 -bit adcs w it h m ult iple x e r 6 _______________________________________________________________________________________ _______________de t a ile d de sc ript ion conve rt e r ope ra t ion the max154/max158 and mx7824/mx7828 use what is commonly called a half-flash conversion technique (figure 3). two 4-bit flash adc sections are used t o achieve an 8-bit result. using 15 comparators, the upper 4-bit ms (most significant) flash adc compare s the unknown input voltage to the reference ladder a nd provides the upper four data bits. an internal dac uses the ms bits to generate an ana log signal from the first flash conversion. a residue v oltage representing the difference between the unknown inp ut and the dac voltage is then compared to the referen ce ladder by 15 ls (least significant) flash comparato rs to obtain the lower four output bits. ope ra t ing se que nc e the operating sequence is shown in figure 4. a con- version is initiated by a falling edge of rd and cs . the comparator inputs track the analog input voltage fo r approximately 1s. after this first cycle, the ms f lash result is latched into the output buffers and the l s con- version begins. int goes low approximately 600ns later, indicating the end of the conversion, and th at the lower four bits are latched into the output buffers . the data can then be accessed using the cs and rd inputs. ___________________digit a l i nt e rfa c e the max154/max158 and mx7824/mx7828 use only chip select (cs ) and read (rd ) as control inputs. a read operation, taking cs and rd low, latches the mul- tiplexer address inputs and starts a conversion (ta ble 1). there are two interface modes, which are determined by the length of the rd input. mode 0, implemented by keeping rd low until the conversion ends, is designed for microprocessors that can be forced into a wait state. in this mode, a conversion is started with a read operation (taking cs and rd low), and data is read when the conversion ends. mode 1, on the other hand , 4-bit dac three- state drivers address latch decode 4-bit flash adc (4lsb) 4-bit flash adc (4msb) 2.5v ref timing and control circuitry mux* v ref + v ref + 16 a0 *max154/mx7824 4-channel mux max158/mx7828 8-channel mux ** ref out on max154/max158 only a1 a2 rdy cs rd ain1 ain4 ain8 ref out** v ref - db7 db6 db5 db4 db3 db2 db1 db0 int max154/mx7824 a1 a0 max158/mx7828 a2 a1 a0 selected channel 00 01 10 11 000 001 010 011 ain1 ain2 ain3 ain4 figure 3. functional diagram table 1. truth table for input channelselection 100 101 110 111 ain5 ain6 ain7 ain8 downloaded from: http:///
does not require microprocessor wait states. a read operation simultaneously initiates a conversion and reads the previous conversion result. i nt e rfa c e m ode 0 figure 5 shows the timing diagram for mode 0 opera- tion. this is used with microprocessors that have w ait state capability, whereby a read instruction is ext end- ed to accommodate slow-memory devices. taking cs and rd low latches the analog multiplexer address and starts a conversion. data outputs db0Cdb7 remain in the high-impedance condition until the conversion i s complete. there are two status outputs: interrupt (int ) and ready (rdy). rdy, an open-drain output (no internal pull- up device), is connected to the processors ready/wait input. rdy goes low on the falling edge of cs and goes high impedance at the end of the conversion, when t he conversion result appears on the data outputs. if t he rdy output is not required, its external pull-up resist or can be omitted. int goes low when the conversion is complete and returns high on the rising edge of cs or rd . i nt e rfa c e m ode 1 mode 1 is designed for applications where the micro - processor is not forced into a wait state. taking c s and rd low latches the multiplexer address and starts a conversion (figure 6). data from the previous con ver- sion is immediately read from the outputs (db0Cdb7) . int goes high at the rising edge of cs or rd and goes low at the end of the conversion. a second read ope r- ation is required to read the result of this conver sion. the second read latches a new multiplexer address and starts another conversion. a delay of 2.5s mus t be allowed between read operations. rdy goes low on the falling edge of cs and goes high impedance at the rising edge of cs . if rdy is not needed, its external pull-up resistor can be omitted. m x 7 8 2 4 /m x 7 8 2 8 cm os, h igh-spe e d, 8 -bit adcs w it h m ult iple x e r _______________________________________________________________________________________ 7 500ns v in is tracked by internal comparators v in is sampled and the four msbs are latched setup time required by the internal comparators prior to starting conversion 600ns rd int going low indicates that conversion is complete and that data can be read 1000ns figure 4. operating sequence data data valid addr valid addr valid int rdy rd analog channel address cs t as t ah t rdy t crd high impedance t css t css t inth t dh t acc2 t as t p t csh figure 5. mode 0 timing diagram downloaded from: http:///
m x 7 8 2 4 /m x 7 8 2 8 _____________ana log conside ra t ions re fe re nc e a nd i nput the v ref + and v r e f - inputs of the converter define the zero and the full-scale of the adc. in other words, the voltage at v ref - is equal to the input voltage that pro- duces an output code of all zeros, and the voltage at v ref + is equal to input voltage that produces an output code of all ones (figure 7). figure 8 shows some possible reference configura- tions. for the max154/max158, a 0.01f bypass capacitor to gnd should be used to reduce the high- frequency output impedance of the internal referenc e. larger capacitors should not be used, as this degra des the stability of the reference buffer. the 2.5v ref erence output is with respect to the gnd pin. bypa ssing a 47f electrolytic and 0.1f ceramic capacitor sho uld be used to bypass the v dd pin to gnd. these capaci- tors must have minimum lead length, since excess le ad length may contribute to conversion errors and inst ability. if the reference inputs are driven by long lines, t hey should be bypassed to gnd with 0.1f capacitors at the reference input pins. cm os, h igh-spe e d, 8 -bit adcs w it h m ult iple x e r 8 _______________________________________________________________________________________ data new data addr valid int rdy rd analog channel address cs t as t ah t rdy t acci t crd t rd t css t rd t rdy t inth t dh t ah t inth t as t p t css t csh addr valid old data t dh t csh t acci figure 6. mode 1 timing diagram 11111111 11111110 11111101 00000011 00000010 00000001 00000000 1 v ref - 23 fs v ref + fs1lsb output code full-scale transition 1lsb = f8 = v ref + - v ref - 256 256 ain input voltage (in terms of lsbs) figure 7. transfer function downloaded from: http:///
i nput curre nt the converters analog inputs behave somewhat diffe r- ently from conventional adcs. the sampled data com- parators take varying amounts of current from the i nput, depending on the cycle they are in. the equivalent cir- cuit of the converter is shown in figure 9a. when t he conversion starts, ain(n) is connected to the ms an d ls comparators. thus, ain(n) is connected to thirty -one 1pf capacitors. to acquire the input signal in approximately 1s, t he input capacitors must charge to the input voltage through the on-resistance of the multiplexer (about 600 ) and the comparators analog switches (2k to 5k per comparator). in addition, about 12pf of stray capacitance must be charged. the input can be mod- eled as an equivalent rc network shown in figure 9b . as r s (source impedance) increases, the capacitors take longer to charge. since the length of the input acquisition time is i nternal- ly set, large source resistances (greater than 100 ) will cause settling errors. the output impedance of an o p- amp is its open-loop output impedance divided by th e loop gain at the frequency of interest. it is impor tant that the amplifier driving the converter input have suffi- cient loop gain at approximately 1mhz to maintain l ow output impedance. i nput filt e ring the transients in the analog input caused by the sa m- pled data comparators do not degrade the converter s performance, since the adc does not look at the input when these transients occur. the comparators outputs track the input during the first 1s of the con- version, and are then latched. therefore, at least 1s will be provided to charge the adcs input capaci- tance. it is not necessary to filter these transien ts with an external capacitor on the ain terminals. sinusoida l i nput s the max154/max158 and mx7824/mx7828 can mea- sure input signals with slew rates as high as 157mv /s to the rated specifications. this means that the an alog input frequency can be as high as 10khz without the aid of an external track/hold. the maximum sampling rate is limited by the conversion time (typical t crd = 2s) plus the time required between conversions (t p = 500ns). it is calculated as: f max = 1 = 1 = 400khz t crd + t p (2.0 + 0.5) s m x 7 8 2 4 /m x 7 8 2 8 cm os, h igh-spe e d, 8 -bit adcs w it h m ult iple x e r _______________________________________________________________________________________ 9 max154 max158 v in gnd v dd ref out v ref + ain x (+) ain x (-) +5v 0.1 m f4 7 m f 0.01 m f v ref - mx7824 mx7828 mx584 v in gnd v dd v ref + ain x (+) ain x (-) +5v 2.5v 0.1 m f 47 m f v ref - max154 max158 mx7824 mx7828 v in gnd v dd v ref + ain x (+) ain x (-) +5v 0.1 m f 47 m f v ref - max154 max158 mx7824 mx7828 v in gnd * current path must still exist from v in(-) to ground v dd v ref + ain x (+) ain x (-) +5v 2.5v 0.1 m f47 m f v ref - * figure 8a. internal reference (max154/max158 only) figure 8b. external reference +2.5v full-scale figure 8c. power supply as reference figure 8d. inputs not referenced to gnd downloaded from: http:///
m x 7 8 2 4 /m x 7 8 2 8 f max permits a maximum sampling rate of 50khz per channel when using the max158/mx7828 and 100khz per channel when using the max154/mx7824. these rates are well above the nyquist requirement of 20k hz sampling rate for a 10khz input bandwidth. bipola r i nput ope ra t ion the circuit in figure 10a can be used for bipolar i nput operation. the input voltage is scaled by an amplif ier so that only positive voltages appear at the adcs inp uts. an external reference should be used for the mx7824 / mx7828, but is not needed with the max154/max158. the analog input range is 4v and the output code i s complementary offset binary. the ideal input/output characteristic is shown in figure 10b. cm os, h igh-spe e d, 8 -bit adcs w it h m ult iple x e r 10 ______________________________________________________________________________________ 1pf c s 12pf c s 2pf 1pf 15 lsb comparators to ls ladder r on 1pf 1pf 16 msb comparators to ms ladder r on r mux r s v in ain1 11111111 11111110 10000010 10000001 01111111 01111110 10000000 00000001 00000000 00000010 0v ain input voltage (lsbs) fs = 8v 1lsb = fs / 256 11111101 +fs 2 -fs + 1lsb 2 r s v in ain1 c s1 2pf c s2 2pf 32pf b mux 600 w r on 350 w max154 max158 ain1 only channel 1 shown v ref + ref out v dd v ref - gnd 11.5 w 3.57k 10.0k 0.01 m f 0.01 m f 0.1 m f 47 m f 16.2k v in +5v cs rdy int db0db7 rd figure 9a. equivalent input circuit figure 10b. transfer function for 4v input operat ion figure 9b. rc network model figure 10a. bipolar 4v input operation downloaded from: http:///
m x 7 8 2 4 /m x 7 8 2 8 cm os, h igh-spe e d, 8 -bit adcs w it h m ult iple x e r ______________________________________________________________________________________ 11 max154 max158 mx7824 mx7828 rd rdy *a2 on max158/mx7828 only. cs a1 a2* a0 5v data bus a15 a0 zbo mreq wait rd db0db7 d0d7 address decode en 5k address bus max158 mx7828 ain2 18 26 +5v 12 23 24 25 15 14 ain8 v ref+ ain1 cs 6 5 28 +5v 27 16 rd a1 db0db7 speech input a0 data v dd ain7 bandpass filter 1 bandpass filter 2 amp v ref- gnd bandpass filter 7 bandpass filter 8 a2 max154 mx7824 ain2 11 24 16 10 +5v 21 22 v ref- v ref+ ain1 int 4 3 2 13 a0 db0db7 v dd v dd sample pulse v ss cs rd ain3 1 ain4 14 gnd 12 a1 a0 a1 15 16 17 mx7226 4 18 3 +15v 6 5 a1 v ref agnd db0db7 2 v out a 1 20 19 v out b v out c v out d a0 dgnd wr figure 12. speech analysis using real-time filteri ng figure 13. 4-channel fast sample and infinite hold figure 11. simple mode 0 interface downloaded from: http:///
maxim cannot assume responsibility for use of any c ircuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the cir cuitry and specifications without notice at any tim e. 12 __________________m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , sunnyva le , ca 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0 ? 1995 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. m x 7 8 2 4 /m x 7 8 2 8 cm os, h igh-spe e d, 8 -bit adcs w it h m ult iple x e r ___________________chip topogra phy _orde ring i nform a t ion (c ont inue d) 1 / 2 24 ssop -40c to +85c mx7824leag 1 24 ssop -40c to +85c mx7824keag 1 28 cerdip -55c to +125c mx7828tq 1 / 2 28 cerdip -55c to +125c mx7828uq 1 28 cerdip -40c to +85c mx7828bq 1 / 2 28 cerdip -40c to +85c mx7828cq 1 28 ssop -40c to +85c mx7828keai 1 / 2 28 ssop -40c to +85c mx7828leai 1 28 plcc 0c to +70c mx7828kp 1 / 2 28 plcc 0c to +70c mx7828lp 1 28 ssop 0c to +70c mx7828kcai 1 / 2 28 ssop 0c to +70c mx7828lcai 1 1 / 2 1 1 / 2 1 1 / 2 1 28 wide so 28 wide so 0c to +70c 0c to +70c 1 / 2 error (lsb) mx7828kcwi mx7828lcwi 28 plastic dip 28 plastic dip 24 cerdip -55c to +125c 0c to +70c 0c to +70c mx7828kn mx7828 ln mx7824tq 24 cerdip 24 cerdip 24 cerdip pin-package temp. range -40c to +85c -40c to +85c -55c to +125c mx7824uq mx7824bq mx7824cq part a1 db3 ain3 (n. c. ) ain4 (n. c. ) ain5 (ain1) ain6 (ain2) ain7 (ain3) ain8 (ain4) a0 int gnd 0. 127" (3. 228mm) 0. 124" (3. 150mm) v ref - v ref + ady a2 (n. c. ) db7 db6 db5 db4 cs v dd a0 db2 db1 ain2 (n. c. ) ain1 (n. c. ) tp (ref out) db0 ( ) are for max154/mx7824 downloaded from: http:///

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